1. Field of Invention
The present invention relates to a stacked semiconductor package, and more particularly, to a stacked semiconductor package using through-silicon vias.
2. Description of the Related Art
Packaging technologies for a semiconductor device have been continuously developed according to demands toward is miniaturization and high capacity, and recently, various technologies for a stacked semiconductor package capable of satisfying miniaturization, high capacity and mounting efficiency are being developed.
The term “stack” that is referred to in the semiconductor industry means a technology of vertically piling at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using a stacking technology, it is possible to realize a product having memory capacity larger than that obtainable through semiconductor integration processes and improve mounting area utilization efficiency.
Among stacked semiconductor packages, a stacked semiconductor package using through-silicon vias has a structure in which through-silicon vias are formed in semiconductor chips and the semiconductor chips are stacked in such a way as to be electrically connected through the through-silicon vias. In the stacked semiconductor package using the through-silicon vias, since electrical connections are formed using through-silicon vias, advantages are provided in that an operation speed can be improved and miniaturization is possible.
However, if a connection failure occurs between the through-silicon vias of the stacked semiconductor chips, signal transfer becomes impossible and the entire stacked semiconductor package cannot be used. As a consequence, manufacturing yield is may markedly decrease.